1. Field of the Invention
The present invention relates to an interface circuit for a serial digital-to-analog converter (hereinafter, simply referred to as a `serial D-A converter`) used in an LSI (Large-Scale Integrated) circuit for audio or the like.
2. Description of the Related Art
In order to convert parallel data generated by a signal generating system as a digital signal into an analog signal through a serial D-A converter, an interface circuit for performing parallel-to-serial conversion is needed between the signal generating system and the serial D-A converter. In a case where the bit width of the parallel data generated by the signal generating circuit is larger than the bit width which can be processed by the serial D-A converter having a processing resolution, it is necessary to cause the bit width per piece of serial data output from the interface circuit as data to be converted into analog data through the serial D-A converter (hereinafter, simply referred to as an `output bit width`) to fit the processing resolution of the serial D-A converter. For this purpose, it is required that, in the interface circuit, the necessary number of bits, starting from the most significant bit, are selected from the parallel data in accordance with the resolution of the serial D-A converter to be used, the selected bits of the parallel data being converted into the serial data to be output. Thereby, it is possible to use serial D-A converters, having various resolutions, with the interface circuit. Thus, it is possible to widely respond to demands for the cost and performance of the entire system. For example, in a case where the signal generating system generates parallel data of 20 bits whereas the resolution of 16 bits is necessary and sufficient for the demand of the performance of the entire system, an inexpensive serial D-A converter can be used as a result of causing the output bit width of the interface circuit to be 16. In a case where the resolution of 20 bits is required for the performance of the entire system, the output bit width of the interface circuit is caused to be 20 and a high-performance serial D-A converter may be used.
As a method of the parallel-to-serial conversion needed in such an interface circuit, a method in which, after the parallel data is loaded in a shift register, the loaded data is output in a serial form as a result of a clock signal being input to the shift register is a general method. FIG. 1 is a block diagram showing an arrangement of an interface circuit in the related art based on the above-mentioned method. This interface circuit includes a shift register 106 for converting the parallel data from the signal generating system into the serial data, a frequency divider 110 for generating a load signal LOAD to be supplied to the shift register 106 and control signals (a word clock signal WCLK and an LR clock signal LRCK) to be supplied to the serial D-A converter, and a load signal generator 112.
The interface circuit shown in FIG. 1 further includes a bit-width specifying register 108 for specifying the output bit width in order to select the necessary number of bits starting from the most significant bit from the parallel data so that the selected bits of data in the form of serial data are output. Further, the interface circuit includes a register 102 for temporarily storing the parallel data supplied from the signal generating system, and a shifter 104 between the register 102 and the shift register 106. In this interface circuit, a value specifying the output bit width is previously set in the bit-width specifying register 108. In a case where the bit width of the input parallel data is larger than the output bit width, the data in the register 102 is shifted by the shifter 104 in accordance with the value set in the bit-width specifying register 108. The data obtained as a result of the data in the register 102 being shifted by the shifter 104 is loaded.in the shift register 106. After the loading, the loaded data is output from the shift register 106 as the serial data DATA in timing of the bit clock signal BCLK supplied to the shift register 106. The number of bits per piece of the serial data (output bit width) is caused to be the bit width specified by the bit-width specifying register 108 as a result of the above-mentioned shifting being performed by the shifter 104.
FIG. 2 is a timing chart showing operations of the above-described interface circuit. In the example shown in FIG. 2, `2.times.`, `4.times.`, . . . , `64.times.` are a twice signal (the signal has twice the period), a four-times signal (the signal has four times the period), . . . , 64-times signal (the signal has 64 times the period), respectively. These signals are obtained as a result of the bit clock signal BCLK undergoing frequency division performed by the frequency divider 110. The 32-times signal `32.times.` and the 64-times signal `64.times.` are input to the serial D-A converter as the word clock signal WCLK and the LR clock signal LRCK, respectively. Further, in this example, it is assumed that the bit width of the parallel data is 20. DATA20, DATA18 and DATA16 shown in FIG. 2 are the signals of the serial data DATA output from the interface circuit in cases where `20`, `18` and `16` are specified by the bit-width specifying register 108 as the output bit widths, respectively. In this interface circuit, the parallel data temporarily stored in the register 102 is loaded in the shift register 106 via the shifter 104 at a timing of the load signal LOAD. At this time, in the case where `20` is specified as the output bit width, the data is loaded in the shift register without undergoing shifting. However, in a case where a value smaller than 20 is specified as the output bit width, the data is shifted in the direction of the least significant bit (LSB) in accordance with the specified value, and the bits of `0` are inserted before the most significant bit (MSB), the number of the bits `0` to be inserted being equal to the number of bits by which the data is shifted, as shown in FIG. 2.
A circuit for performing such a shifting operation includes, as shown in FIG. 3A, selectors each including AND gates and an OR gate. The shifter having the arrangement shown in FIG. 3A is used for outputting the data having any one of the three output bit widths: 16, 18 and 20. In this shifter, shifting by the number of bits determined by selecting signals SEL0 and SEL1 which have values in accordance with the value set in the bit-width specifying register 108 is performed. Specifically, in the case where `16` is selected as the output bit width, SEL0=SEL1=0, as shown in FIG. 3B, and, thereby, the shifting of the data by 4 bits in the direction of the least significant bit is performed. In the case where `18` is selected as the output bit width, SEL0=1 and SEL1=0, and, thereby, the shifting of the data by 2 bits in the direction of the least significant bit is performed. In the case where `20` is selected as the output bit width, SEL0=0 and SEL1=1, and, thereby, no shifting operation is performed.
In the case where adjusting of the output bit width is performed through the shifter such as that shown in FIG. 3A, it is necessary to provide the selector (including the AND gates and OR gate) for each data bit in the shifter. In a case of the interface circuit for the serial D-A converter for audio, for example, because audio data has a bit width on the order of 16 bits to 20 bits in general, it is necessary to provide the selector for this range of the bit width for each data bit. As a result, the circuit scale of the shifter is large.